A power circuit used in a liquid crystal display device driven by a one-line sequential drive method is described below as a first prior-art technique, with reference to FIG. 48. This diagram is basically the same as FIG. 3 of Japanese Patent Application Laid-Open No. 2-150819. In this case, V0 to V5 are in the relationship VD=(V0-V1)=(V1-V2)=(V3-V4) =(V4-V5), where VD is on the order of 1.6 V when the duty ratio is 1/240, for example.
The power source inputs to the liquid crystal display device from the exterior comprises VCC for the logic portions of the driver IC and VEE for creating the liquid crystal panel drive voltages, with GND as a reference potential. VEE is considerably higher than VCC; for example, it is on the order of 20 V to 25 V when the duty ratio is 1/240. Among V0 to V5, VEE is used without modification as V0 and GND as V5. V1+0V4 are obtained by division by resistances R1 to R5 between VEE and GND, the impedances of these outputs are lowered by operational amplifiers (op-amps) OP1 to OP4, and the resultant outputs are used as the remaining V1 to V4. OP1 to OP4 operate at VEE so that VCC is not directly used when the panel drive voltage is generated.
The description now turns to power consumption, with the scan line side being denoted by Y and the data line side being denoted by X. For instance, the scan line electrodes for the panel are called Y electrodes, the driver IC that drives these Y electrodes is called the Y driver, the data line electrodes of the panel are called X electrodes, and the driver IC that drives these X electrodes is called the X driver. The voltage applied to each non-selected Y electrode is V1 or V4. If the non-selected Y electrodes are at V1, the voltage applied to the X electrodes is V0 or V2; if the non-selected Y electrodes are at V4, the voltage applied to the X electrodes is V3 or V5.
With a duty ratio of 1/240, the Y electrode for one line alone is in a selected state; the remaining 239 lines are all in a non-selected state. Therefore, the charging/discharging current that flows between each X electrode and the selected Y electrode is much smaller than the charging/discharging current that flows between each X electrode and non-selected Y electrodes. That is to say, the current consumption of the liquid crystal panel itself is largely due to the charging/discharging currents flowing between each X electrode and the non-selected Y electrodes. Thus the description here concentrates only on the charging/discharging currents flowing between the X electrodes and the non-selected Y electrodes.
Consider, as an example, a case in which the voltage at an X electrode changes from V0 to V2 when the voltage of the non-selected Y electrodes is V1. If the capacitance of the liquid crystal layer between the X and Y electrodes is assumed to be Cpn, a charge of Cpn.times.(V0-V1) flows from V0 and into V1 when the voltage at the X electrode changes from V0 to V1 (see D in FIG. 48). When the voltage at the X electrode then changes from V1 to V2, a charge of Cpn.times.(V1-V2) flows from V1 and into V2 (see E). Since V0-V1=V1-V2 in this example, the charge flowing into V1 and the charge flowing out of V1 are equal. Therefore, the balance of the charges flowing into and out of V1 is zero, so that a charge of Cpn.times.(V0-V2) effectively flows from V0 and into V2 (see F). This charge passes through the op-amp OP2 and eventually flows to GND (see G). However, this charge migrates within OP2 so that it does no effective work along the path to GND, so that thermal losses are generated and OP2 simply becomes hotter. If it is assumed that the panel charging/discharging current in this case is Ipn and GND is 0V, the power consumption due to this Ipn is: Ipn.times.VEE. As is clear from G in FIG. 48, the effective utilization factor of Ipn is: (V0-V2)/VEE. For a duty ratio of 1/240, VEE is 20 V to 25 V when (V0-V2) is on the order of (2.times.1.6) V, so that the effective utilization factor is no more than 16%.
The description now turns to a power circuit used in a liquid crystal display device driven by a four-line simultaneous selection drive method, as a second prior-art technique. The basic concept of the multiple lines selection (MLS) drive method in which a plurality of Y electrodes (row electrodes) are simultaneously selected is disclosed in Document 1 (A Generalized Addressing Technique for RMS Responding Matrix LCDs, Proceedings of the 1988 International Display Research Conf, pp. 80-85) and U.S. Pat. No. 5,262,881. A simple one-line sequential drive has a problem in that contrast is degraded if the response of the liquid crystal is fast, but use of the MLS drive method can solve this problem.
When L lines (where L is a positive integer greater than 1) are simultaneously selected by an MLS drive method, it is necessary to have potentials at a total of three levels for the Y electrodes thereof: VM, and VH and VL positioned with this VM as a center potential. In this case, VM is a non-selection potential and VH and VL are selection potentials. Similarly, potentials at (L+1) levels centered on VM are necessary for the X electrodes. As L increases, the voltage amplitude VH-HL for driving the Y electrodes decreases, but conversely a large voltage amplitude is necessary for driving the X electrodes.
An example of a power circuit that could be considered when using the four-line simultaneous selection drive method is shown in FIG. 49. The voltages necessary for driving the panel are VH and VL that act as selection voltages for the Y electrodes, VM that acts as the non-selection voltage for the Y electrodes, and Vx0 to Vx4 that act as drive voltages for the X electrodes. VM is the center potential of voltages applied to the panel, and the other voltages are in the following relationships: (VH-VM)=(VM-VL) and (Vx0-Vx1) =(Vx1-Vx2)=(Vx2-Vx3)=(Vx3-Vx4). The center potential Vx2 on the X electrode side is at the same potential as VM. For a panel with a 1/240 duty ratio, for example, (VH-VL) is on the order of 25 V and (Vx0-Vx1) is on the order of 1.6 V.
Input power source that is input from the exterior of the liquid crystal display device comprises VCC for the logic portions of the driver ICs and VEE (=VH-VL) for creating the liquid crystal panel drive voltages, with respect to GND as a reference potential (0 V), and, as described above, VEE is a high voltage in comparison with VCC. It should be noted that VDDy and VSSy in FIG. 49 are voltages for the logic portion of the Y driver, and VCC and GND are connected thereto directly. Similarly, VDDx and VSSx are voltages for the logic portion of the X driver, where VDDx-VSSx=VCC if GND is 0 V. The resisting voltage necessary for the X driver is (Vx0-Vx4), which is on the order of 7 V for a panel with a 1/240 duty ratio, for example. VEE and GND are used without modification as VH and VL, respectively. Voltages divided by resistors R1 to R6 between VEE and GND, with their impedances lowered by op-amps OP1 to OP6, are used as Vx0 to Vx4 and VSSx. To ensure that the relationship (VDDx-VSSx)=VCC is satisfied, the resistances of R7 to R10 are set such that R7 =R8 and R9=R10. OP1 to OP6 operate on VEE and VCC has no direct effect on the formation of the panel drive voltages.
The description now turns to the power consumption that occurs when the power circuit of FIG. 49 is used. The voltage applied to each Y electrode when it is not selected is VM and the voltage applied to each X electrode is one of Vx0 to Vx4. In the same manner as in the previously described one-line sequential drive method, a large part of the current consumption of the liquid crystal panel itself is due to the charging/discharging currents flowing between the X electrodes and the non-selected Y electrodes. The power consumption due to the panel charging/discharging current Ipn when GND is 0 V is: Ipn.times.VEE. However, as described previously, the voltage difference between each of Vx0 to Vx4 and VM is much smaller than the voltage difference between VEE and GND. Therefore, the effective utilization factor of Ipn is extremely low, and a large part thereof migrates within the op-amp along a path to GND so that it becomes a thermal loss and the op-amp simply becomes hotter.
Furthermore, if the current consumption in portions such as the logic portion of the X driver is assumed to be IXD, the power consumption thereby is not (IXD.times.VCC) but (IXD.times.VEE). The portion {IXD.times.(VEE-VCC)} inevitably migrates within the op-amp along a path to GND to become a thermal loss so that the op-amp simply becomes hotter. With a method in which a plurality of lines are simultaneously selected, the operating voltage amplitude of the X driver can be made small, but it has not been possible to completely utilize this advantage in the reduction of power consumption in the prior art.
The power circuit for a liquid crystal display device that uses a two-terminal type of non-linear switching element will now be described as a third prior-art technique. This method of driving a liquid crystal display device is disclosed in Japanese Patent Publication No. 5-34655 and a power circuit for use in this method is disclosed in Japanese Patent Publication No. 5-46954 and U.S. Pat. No. 5,101,116. The operation and configuration of this power circuit will now be described with reference to FIG. 50 (drive voltage waveforms shown as FIG. 1A in U.S. Pat. No. 5,101,116) and FIG. 51 (a circuit shown as FIG. 2B therein). In FIG. 50, TPy (where y=1, 2, . . . , n) are the waveforms of voltages that drive Y electrodes, VD2 is a positive-side selection voltage, VS2 is a negative-side selection voltage, VM.sup.+ is a non-selection voltage when VD2 is a selection voltage, and VM.sup.- is a non-selection voltage when VS2 is a selection voltage. (VD2-VS2) is on the order of approximately 40 V and the following relationship is substantially satisfied: (VD2-VM.sup.+)=(VM.sup.- -VS2). In other words, if the center voltage between VD2 and VS2 is VC, VD2 and VS2 are substantially symmetrical with respect to VC, and VM.sup.+ and VM.sup.+ are also substantially symmetrical with respect to VC.
(VM.sup.+ -VM.sup.-) is much smaller than (VD2-VS2). It is constantly necessary with the MLS drive method to have selection voltages on both the positive side and the negative side. In contrast thereto, in a liquid crystal display device using a two-terminal type of non-linear switching element, the selection voltage required at any certain time is one only of VD2 and VS2, so there is no necessity of providing both selection voltages at the same timing. An example of a circuit designed to address this problem by managing with a Y driver resisting voltage that is approximately half of (VD2-VS2) is shown in FIG. 51. A transistor 250 is turned on and another transistor 252 is turned off at a timing in which VD2 is necessary. This causes VD(t) to become VD2, which is a voltage higher than VM.sup.+, and VS(t) to become VS1, which is a voltage higher than VS2, by capacitive coupling. The transistor 252 is turned on and the transistor 250 is turned off, at a timing in which VS2 is necessary. This causes VS(t) to become VS2, which is a voltage lower than VM.sup.-, and VD(t) to become VD1, which is a voltage lower than VD2, by capacitive coupling. Swinging the power voltage applied to the Y driver in this manner makes it possible for a Y-driver resisting voltage of approximately half of (VD2-VS2) to be sufficient, provided that the selection voltage need only be applied to either the positive side or the negative-side at the same timing. A drive method in which the power voltage is made to swing in this fashion is hereinafter called a swinging power source method. At present, this swinging power source method is most commonly used for a liquid crystal panel that uses a two-terminal type of non-linear switching element.
This swinging power source method has an advantage in that an Y-driver resisting voltage of approximately half of (VD2-VS2) will suffice, as described above, but it has a disadvantage in that the power consumption of the liquid crystal display device increases significantly, regardless of this low resisting voltage. One cause of this increase in the power consumption is the presence of all of the parasitic capacitances within the Y driver that are charged and discharged by this swinging voltage, and the shorting currents flow through the Y driver at the same timing as the swinging. Another cause is that the power consumption of the power circuit itself is high and there is no good method of reducing power consumption in the power circuit.
To summarize the above points, each of the power circuits of the configurations shown in FIGS. 48 and 49 has the following problems:
(1) There is a large amount of wasteful power dissipation during the supply of panel charging/discharging currents. PA1 (2) The power consumption is increased even further by current consumption due to the logic portion of the X driver which is also supplied from the high voltage VEE. PA1 (3) Since the high voltage VEE is used as the power source of the op-amps, the power consumption due to the idling current that flows constantly from VEE to GND in the op-amp is large. PA1 (4) Expensive op-amps that have low power consumption and high resisting voltages must be used as the op-amps used in the power circuit. PA1 means for supplying a first input potential on a high-potential side comprised within the input power source as a Gth potential within the first to Nth potentials (where 1&lt;G&lt;N); PA1 means for supplying a second input potential on a low-potential side comprised within the input power source as a Jth potential within the first to Nth potentials (where 1&lt;J&lt;N); PA1 a charge pump circuit which operates based on a given clock signal to thereby supply the first potential on the high-potential side, either directly or via adjustment means; and PA1 a charge pump circuit which operates based on a given clock signal to thereby supply the Nth potential on the low-potential side, either directly or via adjustment means. PA1 the first input potential; the second input potential; a center potential between the first and second input potentials; or, when a potential differing from the first and second input potentials has been generated, a center potential between the generated potential and the first or second input potential. PA1 a charge pump circuit for performing a K-times (where K.gtoreq.2) boosting charge pump operation based on a given clock signal to thereby supply one of the first to Nth potentials, either directly or via adjustment means; and PA1 a charge pump circuit for performing an L/M-times (where L/M is not an integer) dropping or M/L-times boosting charge pump operation based on a given clock signal to thereby supply one of the first to Nth potentials, either directly or via adjustment means. PA1 a charge pump circuit which operates based on a clock signal comprising periodical pulses, to thereby supply one of the first to Nth potentials, either directly or via adjustment means; and PA1 means for stopping charging of a pumping capacitor comprised within the charge pump circuit and charging of a backup capacitor by the pumping capacitor during a period within the pulses. PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first potential on a high-potential side and the Nth potential on a low-potential side, either directly or via adjustment means; and PA1 a charge pump circuit which operates for charging a backup capacitor alternately by a plurality of pumping capacitors on the basis of a given clock signal, to thereby supply an Ith potential within the first to Nth potentials (where 1&lt;I&lt;N), either directly or via adjustment means. PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first to Nth potentials either directly or via an adjustment means; and PA1 means for charging a pumping capacitor comprised within the charge pump circuit and charging a backup capacitor by the pumping capacitor, every horizontal scan period. PA1 a charge pump circuit for performing a K-times (where K.gtoreq.2) boosting or L/M-times (where L/M is not an integer) dropping or M/L-times boosting charge pump operation based on a given clock signal to thereby supply one of the first to Nth potentials, either directly or via adjustment means; and PA1 means for adjusting boosting ratio or dropping ratio of the charge pump circuit. PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first potential on a high-potential side and the Nth potential on a low-potential side, either directly or via adjustment means; and PA1 means for stopping the generation of the first potential or the Nth potential by the charge pump circuit during a given period after the application of the input power source. PA1 means for supplying a first input potential on a high-potential side comprised within the input power source as a Gth potential within the first to Nth potentials (where 1&lt;G&lt;N); PA1 means for supplying a second input potential on a low-potential side comprised within the input power source as a Jth potential within the first to Nth potentials (where 1&lt;J&lt;N); PA1 means for supplying a third input potential on the high-potential side or low-potential side of the first and second input potentials comprised within the input power source as one of the first potential on a high-potential side and the Nth potential on a low-potential side; PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first and Nth potentials, either directly or via adjustment means; and PA1 a charge pump circuit which operates based on a given clock signal to thereby supply an Fth potential (where 1&lt;F&lt;N) on either a high-potential side or a low-potential side of the Gth and Jth potential, either directly or via adjustment means; and PA1 wherein potentials within the first to Nth potentials but which are not one of the first, Fth, Gth, Jth, and Nth potentials are each supplied by a charge pump circuit that operates based on a given clock signal. PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first to Nth potentials either directly or via an adjustment means; and PA1 means for releasing residual charge in circuit portions supplied with a potential obtained from at least one of the first and Nth potentials, when at least one of the following events has occurred: the supply of the input power source is stopped, the supply of the given clock signal is stopped, or a display-off control signal is input. PA1 one of the above described power circuits; PA1 a liquid crystal panel having a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scan line electrodes; PA1 a data line driver for driving the data line electrodes; and PA1 a scan line driver for driving the scan line electrodes. PA1 means for supplying a first input potential on a high-potential side and a second input potential on a low-potential side both comprised within the input power source, as one of the first to Nth potentials; and PA1 a charge pump circuit which operates based on a given clock signal to thereby supply one of the first to Nth potentials either directly or via an adjustment means; and PA1 wherein the first and second input potentials are used as a power source for a logic portion in at least one of the data line driver and the scan line driver. PA1 a charge pump circuit which operates based on a clock signal generated from a latch pulse signal for the data line driver or a shift clock signal for the scan line driver, to thereby supply one of the first to Nth potentials, either directly or via adjustment means.
It is not possible to reduce the power consumption with the power circuit and drive method of the configuration shown in FIG. 51.
This invention was devised in order to solve the above problems and has as an objective thereof the provision of an inexpensive power circuit, liquid crystal display device, and electronic equipment with a low power consumption.